1. Field of Invention
An embodiment of the present invention relates to a test pattern of a semiconductor device, a method of manufacturing the test pattern and a method of testing the semiconductor device by using the test pattern and, more particularly, to a test pattern of a semiconductor device for testing gate pads thereof for alignment, a method of manufacturing the test pattern and a method of testing the semiconductor device by using the test pattern.
2. Description of Related Art
With increasing integration degree of semiconductor devices, it is important to reduce the sizes of components that constitute the semiconductor devices, contacts that electrically couple the components and relevant regions.
As the sizes of the contacts and the components of the semiconductor devices are reduced, overlap margin therebetween may also be reduced. As a result, misalignment may occur between the contacts and the components. In order to test the contacts and components for alignment, a test pattern may be formed in a scribe region of a semiconductor device.